A Reconfigurable Multi Precision MAC with Bin Based FP8 Accumulation for Edge AI
Dixit, A. (2026). "A Reconfigurable Multi Precision MAC with Bin Based FP8 Accumulation for Edge AI." IEEE ISCAS 2026.
CV
Education
- M.Tech. in VLSI Design, IIT Jodhpur, 2025
- CGPA: 9.02
- Thesis: ML Accelerators for NLP Applications
- B.Tech. in EEE, AKGEC, 2022
Work Experience
- May 2024 - Present: RTL Design Engineer
- SandLogic Technologies (Bangalore, India)
- Duties included: RTL development of hardware blocks. Working on low-precision floating-point formats (FP8 E4M3/E5M2, NVFP4) for AI acceleration hardware.
- Mar 2024 - Aug 2024: Hardware Intern
- Jaitra Inc (Remote)
- Duties included: Hardware Prototyping of RISC-V Core (Black Parrot RV64GC) on PYNQ-Z2 and ZCU104. Successfully deployed N-gram language models on FPGA.
- Jul 2024 - Apr 2025: Graduate Teaching Assistant
- IIT Jodhpur
- Duties included: Conducted sessions and assisted students for the Digital ASIC Lab and Hardware-Software Co-Design courses.
- Supervisor: Dr. Binod Kumar
- Sep 2022 - Jul 2023: Junior Research Fellow
- DRDO (SAG) (Jodhpur, India)
- Duties included: Worked on the project “Development of Hardware Trojan Testing Methodology,” researching security vulnerabilities in IC supply chains.
Skills
- Skill 1
- Skill 2
- Sub-skill 2.1
- Sub-skill 2.2
- Sub-skill 2.3
- Skill 3
Publications
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A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference
Dixit, A. (2026). "A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference." IEEE ISCAS 2026.
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Evaluating Functional Coverage of Accelerator Design for DT-based ML Implementations
Dixit, A. (2025). "Evaluating Functional Coverage of Accelerator Design for DT-based ML Implementations." WECON 2025.
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A Methodology for Security-Aware Lightweight Deep Neural Network Acceleration
Dixit, A. (2025). "A Methodology for Security-Aware Lightweight Deep Neural Network Acceleration." VDAT 2025.
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Zero Shot Attention based GPT-2 Accelerator for Resource-Constrained Embedded Platform
Dixit, A. (2025). "Zero Shot Attention based GPT-2 Accelerator for Resource-Constrained Embedded Platform." IEEE Embedded Systems Letters.
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Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation
Dixit, A. (2025). "Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation." ISVLSI 2025.
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Secure Federated Learning for Gate-Level IP Hardware Trojan Detection using Homomorphic Encryption
Dixit, A. (2024). "Secure Federated Learning for Gate-Level IP Hardware Trojan Detection using Homomorphic Encryption." IEEE CCIS 2024.
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A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Networks
Dixit, A. (2024). "A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Networks." IEEE ISES 2024.
Talks
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Conference Proceeding talk 3 on Relevant Topic in Your Field
Conference proceedings talk at Testing Institute of America 2014 Annual Conference, Los Angeles, CA, USA
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Talk 2 on Relevant Topic in Your Field
Talk at London School of Testing, London, UK
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Tutorial 1 on Relevant Topic in Your Field
Tutorial at UC-Berkeley Institute for Testing Science, Berkeley, CA, USA
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Talk 1 on Relevant Topic in Your Field
Talk at UC San Francisco, Department of Testing, San Francisco, CA, USA
Teaching
Service and leadership
- Currently signed in to 43 different slack teams