About Me

Hi, I'm Ayush Dixit, an RTL Design Engineer specializing in AI accelerator architectures and digital hardware design. I currently work at SandLogic Technologies, where I design and develop RTL components for next-generation AI compute systems. Prior to joining SandLogic, I completed my Master's degree from Indian Institute of Technology Jodhpur (IIT Jodhpur). During my M.Tech, my thesis was titled "Hardware Accelerators for NLP Applications" (Link), where I explored efficient hardware architectures for accelerating transformer-based and LSTM natural language processing workloads using Xilinx HLS. I also worked on FPGA prototyping of the Black Parrot RISCV core on the Xilinx ZCU104 platform during my internship at Jaitra Technologies. Before that, I worked as a Junior Research Fellow (JRF) at DRDO (SAG Group), contributing to research in secure and high-performance hardware systems. My interests include AI accelerator design, low-precision arithmetic (FP8 / NVFP4), computer architecture, and hardware security.

Publications

2026

• A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference
  A. Yadav*, N. Bhattacharya*, A. Dixit, S. Sathvik*, B. Kumar
  IEEE International Symposium on Circuits and Systems (ISCAS), 2026
• A Bin-Based FP8 MAC for Edge AI Applications
  A. Dixit , Madan P. , S. Charan Palakurthi
  IEEE International Symposium on Circuits and Systems (ISCAS), 2026

2025

• Evaluating Functional Coverage of Accelerator Design for DT-based ML Implementations
  A. Dixit, R. Kumar, A. Yadav, B. Kumar
  8th World Engineering Conference on Contemporary Technologies (WECON), 2025
• Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation
  A. Yadav, A. Dixit, U. Jana, M. Fujita, B. Kumar
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2025
• Zero-Shot Fused Attention-Based GPT-2 Accelerator for Resource-Constrained Embedded Platform
  A. Yadav, A. Dixit, B. Kumar
  IEEE Embedded Systems Letters, 2025

2024

• A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Network Implementation
  A. Yadav, A. Dixit, U. Jana, B. Kumar
  IEEE International Symposium on Smart Electronic Systems (iSES), 2024
• Secure Federated Learning for Gate-Level IP Hardware Trojan Detection Using Homomorphic Encryption
  A. Raj, A. Dixit, G. S. Bhati, A. Yadav, V. Yadav, V. K. Gupta
  International Conference on Communication, Control, and Intelligent Systems, 2024