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Posts by Collection
portfolio
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publications
A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Networks
Published in IEEE ISES 2024, 2024
Reconfigurable hardware architecture supporting multiple floating-point formats for neural network inference.
Recommended citation: Dixit, A. (2024). "A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Networks." IEEE ISES 2024.
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Secure Federated Learning for Gate-Level IP Hardware Trojan Detection using Homomorphic Encryption
Published in IEEE CCIS 2024, 2024
Federated learning framework with homomorphic encryption for secure hardware trojan detection at gate-level IP.
Recommended citation: Dixit, A. (2024). "Secure Federated Learning for Gate-Level IP Hardware Trojan Detection using Homomorphic Encryption." IEEE CCIS 2024.
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Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation
Published in ISVLSI 2025, 2025
LSTM architecture optimization using CORDIC-based activation functions for keyword spotting.
Recommended citation: Dixit, A. (2025). "Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation." ISVLSI 2025.
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Zero Shot Attention based GPT-2 Accelerator for Resource-Constrained Embedded Platform
Published in IEEE Embedded Systems Letters, 2025
Zero-shot attention mechanism for efficient GPT-2 acceleration on embedded systems.
Recommended citation: Dixit, A. (2025). "Zero Shot Attention based GPT-2 Accelerator for Resource-Constrained Embedded Platform." IEEE Embedded Systems Letters.
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A Methodology for Security-Aware Lightweight Deep Neural Network Acceleration
Published in VDAT 2025, 2025
Methodology for designing security-aware lightweight DNN accelerators.
Recommended citation: Dixit, A. (2025). "A Methodology for Security-Aware Lightweight Deep Neural Network Acceleration." VDAT 2025.
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Evaluating Functional Coverage of Accelerator Design for DT-based ML Implementations
Published in WECON 2025, 2025
Research on evaluating functional coverage of accelerator design for decision tree-based ML implementations.
Recommended citation: Dixit, A. (2025). "Evaluating Functional Coverage of Accelerator Design for DT-based ML Implementations." WECON 2025.
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A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference
Published in IEEE ISCAS 2026, 2026
Graph-based approach for dynamic key-value cache compression to optimize transformer inference efficiency.
Recommended citation: Dixit, A. (2026). "A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference." IEEE ISCAS 2026.
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A Reconfigurable Multi Precision MAC with Bin Based FP8 Accumulation for Edge AI
Published in IEEE ISCAS 2026, 2026
Reconfigurable multiply-accumulate unit supporting multiple precision formats with bin-based FP8 accumulation for edge AI applications.
Recommended citation: Dixit, A. (2026). "A Reconfigurable Multi Precision MAC with Bin Based FP8 Accumulation for Edge AI." IEEE ISCAS 2026.
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talks
Talk 1 on Relevant Topic in Your Field
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Conference Proceeding talk 3 on Relevant Topic in Your Field
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teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
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Teaching experience 2
Workshop, University 1, Department, 2015
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